View STR711F_2948652.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

january 2005 1/39 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. rev. 5 str71xf arm7tdmi ? 16/32-bit mcu with flash, usb, can 5 timers, adc, 10 communications interfaces preliminary data memories ? up to 272 kbytes (256+16k) flash program memory (100,000 cycles endurance, data re- tention 20 years) ? up to 64 kbytes ram ? external memory interface (emi) for up to 4 banks of sram, flash, rom. ? multi-boot capability clock, reset and supply management ? 3.3v application supply and i/o interface ? embedded 1.8v voltage regulator for core supply ? 0 to 16 mhz external main oscillator ? 32 khz external backup oscillator ? internal pll for cpu clock ? up to 50 mhz cpu operating frequency when executing from flash ? realtime clock for clock-calendar function ? 4 power saving modes: slow, wait, stop and standby modes nested interrupt controller ? fast interrupt handling with multiple vectors ? 32 vectors with 16 irq priority levels ? 2 maskable fiq sources up to 48 i/o ports ? 30/32/48 multifunctional bidirectional i/o lines ? 14 ports with inte rrupt capability 5 timers ? 16-bit watchdog timer ? four 16-bit timers each with: 2 input captures, 2 output compares, pwm and pulse counter modes 10 communications interfaces ?2 i 2 c interfaces (1 multiplexed with spi) ? 4 uart asynchronous serial communications interfaces ? smart card iso7816-3 interface on uart1 ? 2 bspi synchronous serial interfaces ? can interface (2.0b active) ? usb v 2.0 full speed (12mbit/s) device func- tion with suspend and resume support ? hdlc synchronous communications inter- face 4-channel 12-bit a/d converter ? conversion time: ? 4 channels: up to 500 hz (2 ms) ? 1 channel: up to 1 khz (1 ms) ? conversion range: 0 to 2.5v development tools support ? jtag with debug mode trigger request table 1. device summary tqfp64 10 x 10 tqfp144 20 x 20 features str710f STR711F str712f z1t6 z2t6 r1t6 r2t6 r1t6 r2t6 flash memory - kbytes 128+16 256+16 128+16 256+16 128+16 256+16 ram - kbytes 16 64 16 64 16 64 peripheral functions can, emi, usb, 48 i/os usb, 30 i/os can, 32 i/os operating voltage 3.0 to 3.6v (optional 1.8v for core) operating temperature -40 to +85c packages tqfp144 20x20 tqfp64 10x10 1
table of contents 39 2/39 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.3 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.4 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3 lvd electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.4 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.5 ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.6 nrstin input filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.7 oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.8 pll electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.9 flash electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.10 external memory bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.11 adc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4 order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 1 note: for detailed information on the str71x f microcontroller memory, registers and peripherals. please refer to the str71xf reference manual.
str71xf - introduction 3/39 1 introduction this preliminary data provides the str71x ordering information, mechanical and electrical device characteristics. for complete information on the str71xf micr ocontroller memory, registers and peripherals. please refer to the str71xf reference manual. for information on programming, erasing and protection of the internal flash memory please refer to the str7 flash programming reference manual for information on the arm7tdmi core please refer to the arm7tdmi technical reference manual. 1.1 overview arm ? core with embedded flash & ram the str71xf series is a family of arm-powered 16/32bit micro-controllers with embedded flash and ram. it combines the high performance arm7tdmi cpu with an extensive range of peripheral functions and enhanced i/o capabilities. all devices have on-chip high-speed single voltage flash memory and high-speed ram. the str71xf family has an embedded arm core and is therefore compatible with all arm tools and software. for information on the arm realview developer kit for st and third-party development tools, please refer to the http://www.st.com website package choice: low pin-count tqfp64 or feature-rich tqfp144 the str71xf family is available in 2 package sizes. the 144-pin version has the full set of all features including can, usb and external memory interface. the two 64-pin versions do not include external memory interface and give you the choice of either can or usb. optional external memory (str710f ) the non-multiplexed 16-bit data/24-bit address bus available on the str710f (tqfp144) supports four 16-mbyte banks of external memory. wait states are programmable individually for each bank allowing different memory types (flash, eprom, rom, sram etc.) to be used to store programs or data. figure 1 shows the general block diagram of the device family. 1
str71xf - introduction 4/39 flexible power management to minimize power consumption, you can program the str71xf to switch to slow, wait for interrupt, stop or standby mode depending on the current system activity in the application. flexible clock control two external clock sources can be used, a main clock and a 32 khz backup clock. the embedded pll allows the internal system clock (up to 50 mhz) to be generated from a main clock frequency of 16 mhz or less. the pll output frequency can be programmed using a wide selection of multipliers and dividers. voltage regulators the str71xf requires an external 3.0-3.6v power supply. there are two internal voltage regulators for generating the 1.8v power supply for the core and peripherals. the main vr is switched off and the low power vr switched on when the application puts the str71xf in standby or low power wait for interrupt (lpwfi) mode. low voltage detectors each voltage regulator has an embedded lvd that monitors the internal 1.8v supply. if the voltage drops below a certain threshold, the lvd will reset the str71xf . on-chip peripherals can interface (str710f and str712f) the can module is compliant with the can spec ification v2.0 part b (active). the bit rate can be programmed up to 1 mbaud. usb interface (str710f and STR711F) the full-speed usb interface is usb v2.0 compliant and provides up to 8 bidirectional/16 unidirectional endpoints, up to 12 mb/s (ful l-speed), support for bulk transfer and usb suspend/resume functions. standard timers each of the four timers have a 16-bit free-running counter with 7-bit prescaler, up to two input capture/output compare functions, a pulse counter function, and a pwm channel with selectable frequency. realtime clock (rtc) the rtc provides a set of continuously running counters driven by a low power 32khz internal oscillator. the rtc can be used as a general timebase or clock/calendar/alarm function. when the str71xf is in standby mode the rtc can be kept running, powered by the low power voltage regulator and driven by the 32khz internal oscillator. 1
str71xf - introduction 5/39 uarts the 4 uarts allow full duplex, asynchronous, communications with external devices with independently programmable tx and rx baud rates up to 625 kb/s. smart card interface uart1 is configurable to function either as a general purpose uart or as an asynchronous smart card interface as defined by iso 7816-3. it includes smart card clock generation and provides support features for synchronous cards. buffered serial peripheral interfaces (bspi) each of the two spis allow full duplex, synchronous communications with external devices, master or slave communication at up to 5.5mb/s in master mode and 4 mb/s in slave mode. i 2 c interfaces the two i 2 c interfaces provide multi-master and slave functions, support normal and fast i 2 c mode (400 khz) and 7 or 10-bit addressing modes. one i 2 c interface is multiplexed with one spi, so either 2xspi+1x i 2 c or 1xspi+2x i 2 c may be used at a time. hdlc interface the high level data link controller (hdlc) unit supports full duplex operation and nrz, nrzi, fm0 or manchester protocols. it has an internal 8-bit baud rate generator. a/d converter the analog to digital converter, converts in single channel or up to 4 channels in single-shot or continuous conversion modes. resolution is 12-bit with a sample rate of 0.5 khz (1 khz in single channel mode). the input voltage range is 0-2.5v. watchdog the 16-bit watchdog timer protects the application against hardware or software failures and ensures recovery by generating a reset. i/o ports the 48 i/o ports are programmable as inputs or outputs. external interrupts up to 14 external interrupts are available for application use or to wake-up the application from stop mode.
str71xf - introduction 6/39 figure 1. str71xf block diagram apb bus usbdp usbdn p0[15:0] i/o port 0 flash memory 144/272k i2c0 i2c1 bspi0 bspi1 uart0 uart1 / uart2 uart3 usb can hdlc apb bridge 1 apb bridge 2 apb bus timer1 timer2 timer3 rtc ext int (xti) watchdog interrupt ctl(eic) a/d power supply prccu/pll ram 16/64k jtag arm7tdmi cpu ext. mem. stdby 2 af 4 af 4 af 2 af 3 af 2 af 2 af 2 af 3 af 4 af 4 af 2 af 4 af a[19:0] d[15:0] rdn wen[1:0] rtcxto rtcxti wakeup jtdi jtck jtms jtrst jtdo ck ckout rstin v18[1:0] v33[6:0] vss[9:0] v18bkp 14 af osc dbgrqs booten vreg avdd avss p1[15:0] i/o port 1 p2[15:0] i/o port 2 timer0 arm7 native bus cs[3:0) 2 af 1 af af: alternate function on i/o port pin interface (emi) a[23:20] smart card
str71xf - introduction 7/39 1.2 related documentation available from www.arm.com: arm7tdmi technical reference manual available from http://www.st.com: str71x reference manual str7 flash programming reference manual an1774 - getting started with str71xf software development an1775 - getting started with str71xf hardware development an1776 - str71xf enhanced interrupt controller an1777 - str71xf memory mapping an1778 - str71xf multi-ice setup an1780 - real time clock with str71xf an1781 - four 7 segment display drive using the str71xf the above is a selected list only, a full li st str71x application notes can be viewed at http://www.st.com .
str71xf - introduction 8/39 1.3 pin description figure 2. str710f package pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 p0.10/u1.rx/u1.tx/scdata rdn p0.11/u1.tx/boot.1 p0.12/scclk vss v33 p2.0/csn.0 p2.1/csn.1 p0.13/u2.rx/t2.ocmpa p0.14/u2.tx/t2.icapa p2.2/csn.2 p2.3/csn.3 p2.4/a.20 p2.5/a.21 p2.6/a.22 booten p2.7/a.23 p2.8 n.c. n.c. vss v33 p2.9 p2.10 p2.11 p2.12 p2.13 p2.14 p2.15 jtdi jtms jtck jtdo jtrstn nu test p1.14/hrxd/i0.sda p1.13/hclk/i0.scl p1.10/usbclk p1.9 v33 vss a.4 a.3 a.2 a.1 a.0 d.15 d.14 d.13 d.12 d.11 d.10 usbdn usbdp p1.12/cantx p1.11/canrx n.c. p1.8 p1.7/t1.ocmpa vssio-pll v33io-pll d.9 d.8 d.7 d.6 d.5 p1.6/t1.ocmpb p1.5/t1.icapb p1.4/t1.icapa p1.3/t3.icapb/ain.3 p1.2/t3.ocmpa/ain.2 n.c. test n.c. v33io-pll n.c. vssio-pll n.c. dbgrqs ckout ck p0.15/wakeup n.c. rtcxti rtcxto stdbyn rstinn n.c. vssbkp v18bkp n.c. n.c. v18 vss18 n.c. d.0 d.1 d.2 d.3 d.4 avdd avss n.c. n.c. n.c. p1.0/t3.ocmpb/ain.0 p1.1/t3.icapa/ain.1 p0.9/u0.tx/boot.0 p0.8/u0.rx/u0.tx p0.7/s1.ssn p0.6/s1.sclk p0.5/s1.mosi vss v33 wen.0 wen.1 a.19 a.18 a.17 a.16 a.15 a.14 v18 vss18 p0.4/s1.miso p0.3/s0.ssn/i1.sda p0.2/s0.sclk/i1.scl p0.1/s0.mosi/u3.rx p0.0/s0.miso/u3.tx a.13 a.12 a.11 a.10 a.9 a.8 a.7 a.6 a.5 v33 vss p1.15/htxd n.c. n.c. tqfp144
str71xf - introduction 9/39 figure 3. str712f package pinout 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 p1.14/hrxd/i0.sda p1.13/hclk/i0.scl p1.10 p1.9 vss p1.12/cantx p1.11/canrx p1.8 p1.7/t1.ocmpa vssio-pll v33io-pll p1.6/t1.ocmpb p1.5/t1.icapb p1.4/t1.icapa p1.3/t3.icapb/ain.3 p1.2/t3.ocmpa/ain.2 v33io-pll vssio-pll ck p0.15/wakeup rtcxti rtcxto nstdby nrstin vssbkp v18bkp v18 vss18 avdd avss p1.0/t3.ocmpb/ain.0 p1.1/t3.icapa/ain.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p0.10/u1.rx/u1.tx/scdata p0.11/u1.tx/boot.1 p0.12/scclk vss p0.13/u2.rx/t2.ocmpa p0.14/u2.tx/t2.icapa booten vss v33 jtdi jtms jtck jtdo njtrst nu test p0.9/u0.tx/boot.0 p0.8/u0.rx/u0.tx p0.7/s1.ssn p0.6/s1.sclk p0.5/s1.mosi vss v18 vss18 p0.4/s1.miso p0.3/s0.ssn/i1.sda p0.2/s0.sclk/i1.scl p0.1/s0.mosi/u3.rx p0.0/s0.miso/u3.tx v33 vss p1.15/htxd tqfp64
str71xf - introduction 10/39 figure 4. STR711F package pinout 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 p1.14/hrxd/i0.sda p1.13/hclk/i0.scl p1.10/usbclk p1.9 vss usbdn usbdp p1.8 p1.7/t1.ocmpa vssio-pll v33io-pll p1.6/t1.ocmpb p1.5/t1.icapb p1.4/t1.icapa p1.3/t3.icapb/ain.3 p1.2/t3.ocmpa/ain.2 v33io-pll vssio-pll ck p0.15/wakeup rtcxti rtcxto nstdby nrstin vssbkp v18bkp v18 vss18 avdd avss p1.0/t3.ocmpb/ain.0 p1.1/t3.icapa/ain.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p0.10/u1.rx/u1.tx/scdata p0.11/u1.tx/boot.1 p0.12/scclk vss p0.13/u2.rx/t2.ocmpa p0.14/u2.tx/t2.icapa booten vss v33 jtdi jtms jtck jtdo njtrst nu test p0.9/u0.tx/boot.0 p0.8/u0.rx/u0.tx p0.7/s1.ssn p0.6/s1.sclk p0.5/s1.mosi vss v18 vss18 p0.4/s1.miso p0.3/s0.ssn/i1.sda p0.2/s0.sclk/i1.scl p0.1/s0.mosi/u3.rx p0.0/s0.miso/u3.tx v33 vss p1.15/htxd tqfp64
str71xf - introduction 11/39 legend / abbreviations for table ? : type: i = input, o = output, s = supply, hiz= high impedance, in/output level: c = cmos 0.3v dd /0.7v dd c t = cmos 0.8v / 2v with input trigger t t = ttl 0.3v dd /0.7v dd with input trigger c/t = programmable levels: cmos 0.3v dd /0.7v dd or ttl 0.8v / 2v port and control configuration: ? input: pu/pd= software enabled internal pull-up or pull down pu= in reset state, the internal 100k ? weak pull-up is enabled. pd = in reset state, the internal 100k ? weak pull-down is enabled. ? output: od = open drain (logic level) pp = push-pull t = true od, (p-buffer and protection diode to v dd not implemented), 5v tolerant. table 2. device pin description pin n pin name type input reset state 1) input output actiive in stdby main function (after reset) alternate function tqfp144 tqfp64 inputlevel interrupt capability od pp 11 p0.10/u1.rx/ u1.tx/ sc.data i/o pd c t x4ma t port 0.10 uart1: receive data input uart1: transmit data output. note: this pin may be used for smartcard datain/dataout or singl e wire uart (half du- plex) if programmed as alternate function output. the pin will be tri-stated except when uart transmission is in progress 2-rd ox external memory interface: active low read signal for external memory. it maps to the oe_n input of the ex- ternal components. 32 p0.11/ boot.1/ u1.tx i/o pd c t 4ma x x port 0.11 select boot con- figuration input uart1: transmit data output. 4 3 p0.12/sc.clk i/o pd c t 4ma port 0.12 smartcard reference clock output 54v ss s ground voltage for digital i/os 6-v 33 s supply voltage for digital i/os 7-p2.0/cs .0 i/o pu c t 8ma x x port 2.0 external memory interface: select memory bank 0 output note: this pin is forced to output mode at re- set to allow boot from external memory 8-p2.1/cs .1 i/o pu 2) c t 8ma x x port 2.1 external memory interface: select memory bank 1 output 95 p0.13/u2.rx/ t2.ocmpa i/o pu c t x4ma x x port 0.13 uart2: receive data input timer2: output compare a output 10 6 p0.14/u2.tx/ t2.icapa i/o pu c t 4ma x x port 0.14 uart2: transmit data output timer2: input capture a input 11 - p2.2/cs .2 i/o pu 2) c t 8ma x x port 2.2 external memory interface: select memory bank 3 output
str71xf - introduction 12/39 12 - p2.3/cs .3 i/o pu 2) c t 8ma x x port 2.3 external memory interface: select memory bank 4 output 13 - p2.4/a.20 i/o pd 3) c t 8ma x x port 2.4 external memory in terface: address bus 14 - p2.5/a.21 i/o pd 3) c t 8ma x x port 2.5 15 - p2.6/a.22 i/o pd 3) c t 8ma x x port 2.6 16 7 booten i c t boot control input. enabl es sampling of boot[1:0] pins 17 - p2.7/a.23 i/o pd 3) c t 8ma x x port 2.7 external memo ry interface: address bus 18 - p2.8 i/o pu c t x 4ma x x port 2.8 external interrupt int2 19 - n.c. not connected (not bonded) 20 - n.c. not connected (not bonded) 21 8 v ss s ground voltage for digital i/os 22 9 v 33 s supply voltage for digital i/os 23 - p2.9 i/o pu c t x 4ma x x port 2.9 external interrupt int3 24 - p2.10 i/o pu c t x4ma x x port 2.10 external interrupt int4 25 - p2.11 i/o pu c t x4ma x x port 2.11 external interrupt int5 26 - p2.12 i/o pu c t 4ma x x port 2.12 27 - p2.13 i/o pu c t 4ma x x port 2.13 28 - p2.14 i/o pu c t 4ma x x port 2.14 29 - p2.15 i/o pu c t 4ma x x port 2.15 30 10 jtdi i t t jtag data input. external pull-up required. 31 11 jtms i t t jtag mode selection input. external pull-up required. 32 12 jtck i c jtag clock input. external pull-up or pull-down re- quired. 33 13 jtdo o 8ma x jtag data output. note: reset state = hiz. 34 14 jtrst it t jtag reset input. exte rnal pull-up required. 35 15 nu reserved, must be forced to ground. 36 16 test reserved, must be forced to ground. 37 - n.c. not connected (not bonded) 38 - test reserved, must be forced to ground. table 2. device pin description pin n pin name type input reset state 1) input output actiive in stdby main function (after reset) alternate function tqfp144 tqfp64 inputlevel interrupt capability od pp
str71xf - introduction 13/39 39 - n.c. not connected (not bonded) 40 17 v 33io-pll s supply voltage for digital i/o circuitry and for pll refer- ence 41 - n.c. not connected (not bonded) 42 18 v ssio-pll s ground voltage for digital i/o circuitry and for pll ref- erence 43 - n.c. not connected (not bonded) 44 - dbgrqs i c t debug mode request input (active high) 45 - ckout o 8ma x clock output (f pclk2 ) note: enabled by ckdis register in apb bridge 2 46 19 ck i c reference clock input 47 20 p0.15/wake- up iput t x4ma x port 0.15 wakeup from standby mode input. 48 - n.c. not connected (not bonded) 49 21 rtcxti realtime clock input and input of 32 khz oscillator am- plifier circuit 50 22 rtcxto output of 32 khz o scillator amplifier circuit 51 23 stdby i/o c t 4ma x x input: hardware standby mode entry input active low. caution: external pull-up to v 33 required to select nor- mal mode. output: standby mode active low output following soft- ware standby mode entry. note : in standby mode all pins are in high impedance except those marked active in stdby 52 24 rstin ic t x reset input 53 - n.c. not connected (not bonded) 54 25 v ssbkp s x stabilisation for low power voltage regulator. 55 26 v 18bkp sx stabilisation for low power voltage regulator. requires external capacitors of at least 1f between v 18bkp and v ss18bkp . see figure 5 . note: if the low power voltage regulator is bypassed, this pin can be connected to an external 1.8v supply. 56 - n.c. not connected (not bonded) 57 - n.c. not connected (not bonded) 58 27 v 18 s stabilisation for main voltage regulator. requires exter- nal capacitors of at least 10f + 33nf between v 18 and v ss18 . see figure 5 . 59 28 v ss18 s stabilisation for main voltage regulator. 60 - n.c. not connected (not bonded) table 2. device pin description pin n pin name type input reset state 1) input output actiive in stdby main function (after reset) alternate function tqfp144 tqfp64 inputlevel interrupt capability od pp
str71xf - introduction 14/39 61 - d.0 i/o 8ma external memory interface: data bus 62 - d.1 i/o 8ma 63 - d.2 i/o 8ma 64 - d.3 i/o 8ma 65 - d.4 i/o 8ma 66 29 v dda s supply voltage for a/d converter 67 30 v ssa s ground voltage for a/d converter 68 - n.c. not connected (not bonded) 69 - n.c. not connected (not bonded) 70 - n.c. not connected (not bonded) 71 31 p1.0/t3.oc- mpb/ain.0 i/o pu c t 4ma x x port 1.0 timer 3: output compare b adc: analog input 0 72 32 p1.1/t3.ica- pa/t3.ext- clk/ain.1 i/o pu c t 4ma x x port 1.1 timer 3: input capture a or ex- ternal clock input adc: analog input 1 73 33 p1.2/t3.ocm- pa/ain.2 i/o pu c t 4ma x x port 1.2 timer 3: output compare a adc: analog input 2 74 34 p1.3/ t3.icapb/ ain.3 i/o pu c t 4ma x x port 1.3 timer 3: input capture b adc: analog input 3 75 35 p1.4/t1.ica- pa/t1.ext- clk i/o pu c t 4ma x x port 1.4 timer 1: input capture a timer 1: external clock input 76 36 p1.5/ t1.icapb i/o pu c t 4ma x x port 1.5 timer 1: input capture b 77 37 p1.6/t1.oc- mpb i/o pu c t 4ma x x port 1.6 timer 1: output compare b 78 - d.5 i/o 8ma external memory interface: data bus 79 - d.6 i/o 8ma 80 - d.7 i/o 8ma 81 - d.8 i/o 8ma 82 - d.9 i/o 8ma 83 38 v 33io-pll s supply voltage for digital i/o circuitry and for pll refer- ence 84 39 v ssio-pll s ground voltage for digital i/o circuitry and for pll ref- erence 85 40 p1.7/t1.ocm- pa i/o pu c t 4ma x x port 1.7 timer 1: output compare a 86 41 p1.8 i/o pd c t 4ma x x port 1.8 87 - n.c. not connected (not bonded) table 2. device pin description pin n pin name type input reset state 1) input output actiive in stdby main function (after reset) alternate function tqfp144 tqfp64 inputlevel interrupt capability od pp
str71xf - introduction 15/39 88 42 p1.11/canrx i/o pu c t x4ma x x port 1.11 can: receive data input note: on str710 and str712 only 89 43 p1.12/cantx i/o pu c t x4ma x x port 1.12 can: transmit data output note: on str710 and str712 only 90 42 usbdp i/o c t usb bidirectional data (dat a +). reset state = hiz note: on str710 and str711 only this pin requires an external pull-up to v 33 to maintain a high level. 91 43 usbdn i/o c t usb bidirectional data (dat a -). reset state = hiz note: on str710 and str711 only. 92 - d.10 i/o 8ma external memory interface: data bus 93 - d.11 i/o 8ma 94 - d.12 i/o 8ma 95 - d.13 i/o 8ma 96 - d.14 i/o 8ma 97 - d.15 i/o 8ma 98 - a.0 o 8ma external memory in terface: address bus 99 - a.1 o 8ma 100 - a.2 o 8ma 101 - a.3 o 8ma 102 - a.4 o 8ma 103 44 v ss s ground voltage for digital i/o circuitry 104 - v 33 s supply voltage for digital i/o circuitry 105 45 p1.9 i/o pd c t 4ma x x port 1.9 106 46 p1.10/usb- clk i/o pu c/t 4ma x x port 1.10 usb: 48 mhz clock input 107 47 p1.13/hclk/ i0.scl i/o pu c t x4ma x x port 1.13 hdlc: reference clock input i2c clock 108 48 p1.14/hrxd/ i0.sda i/o pu c t x4ma x x port 1.14 hdlc: receive data input i2c serial data 109 - n.c. not connected (not bonded) 110 - n.c. not connected (not bonded) 111 49 p1.15/htxd i/o pu c t x4ma x x port 1.15 hdlc: transmit data output 112 50 v ss s ground voltage for digital i/o circuitry 113 51 v 33 s supply voltage for digital i/o circuitry table 2. device pin description pin n pin name type input reset state 1) input output actiive in stdby main function (after reset) alternate function tqfp144 tqfp64 inputlevel interrupt capability od pp
str71xf - introduction 16/39 114 - a.5 o 8ma external memory in terface: address bus 115 - a.6 o 8ma 116 - a.7 o 8ma 117 - a.8 o 8ma 118 - a.9 o 8ma 119 - a.10 o 8ma 120 - a.11 o 8ma 121 - a.12 o 8ma 122 - a.13 o 8ma 123 52 p0.0/s0.miso/ u3.tx i/o pu c t 4ma x x port 0.0 spi0 master in/ slave out data uart3 transmit data output note: programming af function selects uart by default. bspi must be enabled by spi_en bit in the bootcr register. 124 53 p0.1/s0.mosi/ u3.rx i/o pu c t x4ma x x port 0.1 bspi0: master out/slave in data uart3: receive data in- put note: programming af function selects uart by default. bspi must be enabled by spi_en bit in the bootcr register. 125 54 p0.2/ s0.sclk/ i1.scl i/o pu c t x4ma x x port 0.2 bspi0: serial clock i2c1: serial clock note: programming af function selects i2c by default. bspi must be enabled by spi_en bit in the bootcr register. 126 55 p0.3/s0.ss / i1.sda i/o pu c t 4ma x x port 0.3 spi0: slave se- lect input active low. i2c1: serial data note: programming af function selects i2c by default. bspi must be enabled by spi_en bit in the bootcr register. 127 56 p0.4/s1.miso i/o pu c t 4ma x x port 0.4 spi1: mast er in/slave out data 128 57 v ss18 s stabilisation for main voltage regulator. 129 58 v 18 s stabilisation for main voltage regulator. requires exter- nal capacitors of at least 10f + 33nf between v 18 and v ss18 . see figure 5 . 130 - a.14 o 8ma external memory in terface: address bus 131 - a.15 o 8ma 132 - a.16 o 8ma 133 - a.17 o 8ma 134 - a.18 o 8ma 135 - a.19 o 8ma table 2. device pin description pin n pin name type input reset state 1) input output actiive in stdby main function (after reset) alternate function tqfp144 tqfp64 inputlevel interrupt capability od pp
str71xf - introduction 17/39 1. the reset configuration of the i/o ports is ipupd (input pull-up/pull down). refer to table 3, ?port bit configuration table,? on page 18 . the port bit configuration at reset is pc0=1, pc1=1, pc2=0. the port data register bit (pd) value depends on the pu/pd column which specifies whether the pull-up or pull-down is enabled at reset 2. in reset state, these pins configured as input pu/pd with weak pull-up enabled. they must be configured by software as alternate function (see table 3, ?port bit configuration table,? on page 18 ) to be used by the external memory interface. 3. in reset state, these pins configured as inpu t pu/pd with weak pull-down enabled to output address 0x0000 0000 using the external memory interface. to access memory banks greater than 1mbyte, they need to be configured by software as alternate function (see table 3, ?port bit configuration table,? on page 18 ). 136 - we .1 o 8ma external memory interface: active low msb write ena- ble output 137 - we .0 o 8ma external memory interface: active low lsb write enable output 138 - v 33 s supply voltage for digital i/os 139 59 v ss s ground voltage for digital i/os 140 60 p0.5/s1.mosi i/o pu c t 4ma x x port 0.5 spi1: master out/slave in data 141 61 p0.6/s1.sclk i/o pu c t x 4ma x x port 0.6 spi1: serial clock 142 62 p0.7/s1.ss i/o pu c t 4ma x x port 0.7 spi1: slave select input active low 143 63 p0.8/u0.rx/ u0.tx i/o pd c t x4ma t port 0.8 uart0: receive data input uart0: transmit data output. note: this pin may be used for single wire uart (half duplex) if programmed as al ternate function output. the pin will be tri-stated e xcept when uart transmis- sion is in progress 144 64 p0.9/u0.tx/ boot.0 i/o pd c t 4ma x x port 0.9 select boot con- figuration input uart0: transmit data output table 2. device pin description pin n pin name type input reset state 1) input output actiive in stdby main function (after reset) alternate function tqfp144 tqfp64 inputlevel interrupt capability od pp
str71xf - introduction 18/39 figure 5. recommended external connection of v 18 and v 18bkp pins table 3. port bit configuration table port configuration registers (bit) values pc0(n) 01010101 pc1(n) 00110011 pc2(n) 00001111 configuration hiz/ain in in ipupd out out af af output tri tri tri wp od pp od pp input ain ttl cmos cmos n.a. n.a. cmos cmos notes: af: alternate function od: open drain ain: analog input out: output ipupd: input pull up /pull down pp: push-pull cmos: cmos input levels tri: tristate hiz: high impedance ttl: ttl input levels in: input wp: weak push-pull n.a. not applicable. in output mode, a read access to the port gets the output latch value). tqfp144 tqfp64 58 57 27 129 128 33 nf 59 10 f 10 f 33 nf 54 55 1f 25 26 1f 28 58 v 18bkp v 18 v 18 v 18 v 18 v 18bkp
str71xf - introduction 19/39 1.4 memory mapping figure 6. memory map apb bridge 2 regs addressable memory space 0 1 2 3 4 4k 5 6 7 0x2000 0000 0x4000 0000 0x6000 0000 0x8000 0000 0xa000 0000 0xc000 0000 0xe000 0000 0xffff ffff 0xc000 0000 0xc000 1000 0xc000 2000 0xc000 3000 0xc000 4000 0xc000 5000 0xc000 6000 0xc000 7000 0xc000 8000 0xc000 9000 0xc000 a000 0xc000 b000 0xc000 c000 0xe000 1000 0xe000 2000 0xe000 3000 0xe000 4000 0xffff ffff 0x0000 0000 apb memory space 4 gbytes flash/ram/emi extmem 1k 0xffff f800 4k eic 0xffff f800 apb bridge 1 regs reserved flash 256k+16k+32b b0f0 b0f4 b0f5 b0f6 b1f0 0x4000 0000 8k 8k 32k 64k 64k 64k flash memory space 272 kbytes + regs 0x4000 4000 0x4000 6000 0x4001 0000 0x4002 0000 0x4003 0000 reserved 4k (*) flash aliased at 0x0000 0000h by system decoder for booting with valid instruction upon reset from block b0 (8 kbytes) 0xe000 0000 0xe000 5000 0xe000 6000 0xe000 7000 0xe000 8000 0xe000 9000 0xe000 a000 0xe000 b000 i 2 c 0 i2c 1 reserved uart 0 uart 1 uart 2 uart 3 usb + ram bspi 0 bspi 1 xti reserved ioport 1 ioport 2 adc clkout timer 3 rtc wdg 0xe000 e000 0xe000 d000 0xe000 c000 0xc000 d000 0xc000 e000 prccu 1k can b0f7 0x400c 0000 0x400c 4000 0x4010 0000 reserved 8k timer 0 timer 1 timer 2 reserved reserved hdlc + ram reserved 0xc001 0000 0xc000 f000 b1f1 0x400c 2000 reserved 0x4004 0000 8k 0x4010 dfbf 20b flash registers 0x4000 2000 ram 64k apb1 apb2 eic b0f2 b0f1 4k 4k 4k 4k 4k 4k 4k 4k 4k 4k 4k 4k 4k 4k 4k reserved reserved ioport 0 64k 64k 4k 4k 4k 4k 4k 4k 4k 4k 4k 4k 4k 4k 4k 4k 4k 4k b0f3 8k 8k 0x4000 8000
str71xf - introduction 20/39 figure 7. external memory map drawing not in scale addressable memory space 0 1 2 3 4 5 6 7 0x2000 0000 0x4000 0000 0x6000 0000 0x8000 0000 0xa000 0000 0xc000 0000 0xe000 0000 0xffff ffff 0x0000 0000 4 gbytes flash/ram/emi extmem 0xffff f800 reserved flash bcon3 bank3 bank2 0x6000 0000 16m 16m 16m 16m 0x6200 0000 0x6400 0000 0x6600 0000 reserved prccu bank1 ram apb1 apb2 eic bcon1 bcon2 bcon0 0x6c00 0000 0x6c00 0004 0x6c00 0008 0x6c00 000c register register register register bank0 external memory space 64 mbytes csn.0 csn.1 csn.2 csn.3 0x60ff ffff 0x62ff ffff 0x64ff ffff 0x66ff ffff
str71xf - electrical characteristics 21/39 2 electrical characteristics 2.1 absolute maximum ratings this product contains devices to protect the inputs against damage due to high static voltages. however, it is advisable to take normal precautions to avoid application of any voltage higher than the specified maximum rated voltages. for proper operation, it is recommended that v in and v o be higher than v ss and lower than v 33 . reliability is enhanced if unused input s are connected to an appropriate logic voltage level (v 33 or v ss ). table 4. absolute maximum ratings. note stresses exceeding above listed recommended ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. during overload conditions (v in >v 33 or v in str71xf - electrical characteristics 22/39 2.2 operating conditions note ram data retention is guaranteed with v 33 not below 2.7 volt, with the device in low power mode (stop or wait for interrupt). 2.3 lvd electrical characteristics v 33 = 3.3 10%, t a = -40 / 85 c unless otherwise specified. table 5. lvd electrical characteristics symbol parameter value unit min max v 33 digital supply voltage fo r i/o circuitry 3.0 3.6 v v 33io-pll digital supply voltage for i/o circ uitry and for pll reference 3.0 3.6 v v 18bkp external supply voltage for backup bl ock (voltage regulat or off) 1.4 1.8 v av dd analog supply voltage for the a/d converter v 33 v 33 v t a ambient temperature under bias ?40 +85 c t j junction temperature under bias ?40 +105 c symbol parameter test conditions value unit min typ max v it lvd threshold main and lp lvds 1.3 1.45 v
str71xf - electrical characteristics 23/39 2.4 dc electrical characteristics v 33 = 3.3v 10%, t a = -40 / 85 c unless otherwise specified. table 6. dc electrical characteristics symbol parameter comment value unit min typ max v ih input high level cmos with or w/o hysteresis 0.7v 33 v input high level p0.15 (wakeup) only 1.8 v v il input low level cmos with or w/o hysteresis 0.3v 33 v input low level p0.15 (wakeup) only 0.7 v v hys input hysteresis cmos schmitt trigger 0.4 0.8 1.2 v input hysteresis schmitt trigger p0.15 (wakeup) only 0.3 0.5 v v oh output high level high current pins push pull, i oh = 8ma v 33 ? 0.8 v output high level standard current pins push pull, i oh = 4ma v 33 ? 0.8 v v ol output low level high current pins push pull, i ol = 8ma 0.4 v output low level standard current pins push pull, i ol = 4ma 0.4 v r wpu weak pull-up resistor measured at 0.5v 33 100 k ? r wpd weak pull-down resi stor measured at 0.5v 33 100 k ?
str71xf - electrical characteristics 24/39 2.5 ac electrical characteristics v 33 = 3.3v 10%, t a = 27 c unless otherwise specified. note i ddrun is the power consumption in applications exploiting the full performances of the core (running at the maximum frequency). note i ddwfi is the power consumption with plls off, vreg and flash on. this guarantees the minimum interrupt response time. note i ddlp is the power consumption with plls, main vreg and flash off. 1) refer to apbn_ckdis register description. table 7. power consumption symbol parameter conditions value unit min typ max i ddrun run mode current mclk=50 mhz see table 8 100 ma i ddwfi wfi mode current 1 mhz system clock 3 6 ma i ddlp lpwfi mode current 32 khz system clock 200 a i ddstp stop mode current main vreg of f, flash in power-down 100 a i ddsb1 standby mode current lp vreg and 32khz osc on 15 30 a i ddsb0 standby mode current lp vreg, lvd, 32khz osc bypassed 3 10 a table 8. i ddrun typical data measurements, t a =25c frequency all peripheral clocks enabled 1) (reset configuration) all peripheral clocks disabled 1) unit ram execution flash execution ram execution flash execution mclk=1 mhz pclk=1 mhz 15 15 11 11 ma mclk=8 mhz pclk=8 mhz 19 20 15 17 mclk=16 mhz pclk=8 mhz 23 27 19 23 mclk=48 mhz pclk=6 mhz 43 53 40 50 mclk=64 mhz pclk=8 mhz 53 n/a 48 n/a
str71xf - electrical characteristics 25/39 v 33 = 3.3v 10%, t a = -40 / 85 c unless otherwise specified. 2.6 nrstin input filter characteristics v 33 = 3.3v 10%, t a = -40 / 85 c unless otherwise specified. table 10. nrstin input filt er characteristics table 9. ac electrical characteristics symbol parameter conditions value unit min typ max f mclk cpu frequency executing from ram or external memory 66 mhz executing from flash 50 executing from flash with rww 45 burst mode disabled (flashlp bit =1) 33 f pclk peripheral clock for apb 33 f ck clock input pin 16 symbol parameter conditions value unit min typ max t fr nrstin input filtered pulse 500 ns t nfr nrstin input not filtered pulse 1.2 s
str71xf - electrical characteristics 26/39 2.7 oscillator electrical characteristics v 33 = 3.3 10%, t a = -40 / 85 c unless otherwise specified. figure 8. crystal oscillator and resonator table 11. oscillator electrical characteristics 2.8 pll electrical characteristics v 33 = 3.3 10%, v 33iopll = 3.3 10%, t a = -40 / 85 c unless otherwise specified. table 12. pll1 electrical characteristics symbol parameter test conditions value unit min typ max g m oscillator transconductance 8 a/v t stup oscillator start-up time stable v 33 2.5 s symbol parameter test conditions value unit min typ max f pllclk1 pll output clock f pll1 x 24 165 mhz f pll1 pll input clock fref_range = 0 1.5 3.0 mhz fref_range = 1 mx[1:0]=?00? or ?01? 3.0 8.25 mhz fref_range = 1 mx[1:0]=?10? or ?11? 3.0 6 mhz c l c l rtcxti rtcxto r s rtcxti rtcxto device device
str71xf - electrical characteristics 27/39 table 13. pll2 electrical characteristics f free1 pll free running frequency fref_range = 0 mx[1:0]=?01? or ?11? 1mhz fref_range = 0 mx[1:0]=?00? or ?10? 2mhz fref_range = 1 mx[1:0]=?01? or ?11? 2mhz fref_range = 1 mx[1:0]=?00? or ?10? 4mhz t lock1 pll lock time fref_range = 0 stable input clock stable v 33iopll , v 18 300 s fref_range = 1 stable input clock stable v 33iopll , v 18 600 s ? t jitter1 pll jitter (peak to peak) t pll = 4 mhz, mx[1:0]=?11? global output division = 32 (output clock = 2 mhz) 0.7 2 ns symbol parameter test conditions value unit min typ max f pllclk2 pll output clock f pll x 28 140 mhz f pll2 pll input clock fref_range = 0 1.5 3.0 mhz fref_range = 1 3.0 5 mhz t lock2 pll lock time fref_range = 0 stable input clock stable v 33iopll , v 18 300 s fref_range = 1 stable input clock stable v 33iopll , v 18 600 s ? t jitter2 pll jitter (peak to peak) t pll = 4 mhz, mx[1:0]=?11? global output division = 32 (output clock = 2 mhz) 0.7 2 ns symbol parameter test conditions value unit min typ max
str71xf - electrical characteristics 28/39 2.9 flash electrical characteristics v 33 = 3.3 10%, t a = -40 / 85 c unless otherwise specified. table 14. flash program/erase characteristics 1 note c 0 : t a = 85 c after 0 cycles c max : t a = 85 c after max number of cycles table 15. flash program/erase characteristics 2 symbol parameter test conditions value unit typ max(c 0 ) max(c max ) t pw word program 40 s t pdw double word program 60 s t pb0 bank 0 program (256k) double word program 1.6 2.1 4.3 s t pb1 bank 1 program (16k) double word program 130 170 300 ms t es sector erase (64k) not preprogrammed preprogrammed 2.3 1.9 4.0 3.3 4.9 4.1 s t es sector erase (8k) not preprogrammed preprogrammed 0.7 0.6 1.1 1.0 1.36 1.26 s t es bank 0 erase (256k) not preprogrammed preprogrammed 8.0 6.6 13.7 11.2 17.2 14.0 s t es bank 1 erase (16k) not preprogrammed preprogrammed 0.9 0.8 1.5 1.3 1.87 1.66 s t rpd recovery from power-down 20 s t psl program suspend latency 10 s t esl erase suspend latency 300 s symbol parameter conditions value unit min typ max endurance 10 kcycles endurance (bank1 sectors) 100 kcycles data retention 20 years t esr erase suspend rate min time from erase resume to next erase suspend 20 ms
str71xf - electrical characteristics 29/39 2.10 external memory bus timing v 33 = 3.3 10%, t a = -40 / 85 c unless otherwise specified. the tables below use a variable which is derived from the emi_bconn registers (described in the str71x reference manual) and represents the special characteristics of the programmed memory cycle. table 16. emi read operation see figure 9 , figure 10 , figure 11 and figure 12 for related timing diagams. table 17. emi write operation see figure 13 , figure 14 , figure 15 and figure 16 for related timing diagrams. symbol parameter value t mclk cpu clock period 1 / f mclk t c memory cycle time wait states t mclk x (1 + [c_length]) symbol parameter test conditions value unit min typ max t rcr read to csn removal time t mclk ns t rp read pulse time t c ns t rds read data setup time 3 ns t rdh read data hold time 3 ns t ras read address setup time 1.3*t mclk ns t rah read address hold time 3 ns t rat read address turnaround time 3 ns t rrt rdn turnaround time t mclk ns symbol parameter test conditions value unit min typ max t wcr wen to csn removal time t mclk ns t wp write pulse time t c ns t wds write data setup time 3 ns t wdh write data hold time 3 ns t was write address setup time 1.3*t mclk ns t wah write address hold time 3 ns t wat write address turnaround time 3 ns t wwt wen turnaround time t mclk ns
str71xf - electrical characteristics 30/39 figure 9. read cycle timing: 16-bit read on 16-bit memory figure 10. read cycle timing: 32-bit read on 16-bit memory see table 16 for read timing data. csn.x wen.x a[23:0] d[15:0] rdn (input) address data input t rds t rdh t rcr t ras t rah t rp csn.x wen.x a[23:0] d[15:0] rdn (input) address data input t rds t rdh t rcr t ras t rah data input t rds t rdh t rrt t rah address t rat t rp t rp
str71xf - electrical characteristics 31/39 figure 11. read cycle timing: 16-bit read on 8-bit memory figure 12. read cycle timing: 32-bit read on 8-bit memory see table 16 for read timing data. csn.x wen.x a[23:0] d[7:0] rdn (input) address data input t rds t rdh t rcr t ras t rah data input t rds t rdh t rrt t rah address t rat t rp t rp csn.x wen.x a[23:0] d[7:0] rdn (input) address data input t rds t rdh t rcr t ras t rah data input t rds t rdh t rrt t rah address t rat t rp t rp t rrt t rah address t rat t rp data input t rds t rdh t rrt t rah address t rat t rp data input t rds t rdh
str71xf - electrical characteristics 32/39 figure 13. write cycle timing: 16-bit write on 16-bit memory figure 14. write cycle timing: 32-bit write on 16-bit memory see table 17 for write timing data. csn.x wen.x a[23:0] d[15:0] rdn (output) address data output t wdh t wcr t was t wds t wah t wp csn.x wen.x a[23:0] d[15:0] rdn (output) address data output t wds t wdh t wcr t was t wah t wp data output t wds t wdh t wwt t wah address t wat t wp
str71xf - electrical characteristics 33/39 figure 15. write cycle timing: 16-bit write on 8-bit memory figure 16. write cycle timing: 32-bit write on 8-bit memory see table 17 for write timing data. csn.x wen.x a[23:0] d[7:0] rdn (output) address data output t wds t wdh t wcr t was t wah t wp data output t wds t wdh t wwt t wah address t wat t wp csn.x wen.x a[23:0] d[7:0] rdn (output) address data output t wds t wdh t wcr t was t wah t wp data output t wds t wdh t wwt t wah address t wat t wp t wwt t wah address t wat t wp data output t wds t wdh t wwt t wah address t wat t wp data output t wds t wdh
str71xf - electrical characteristics 34/39 2.11 adc electrical characteristics v 33 = 3.3 10%, av dd = 3.3 10%, t a = -40 / 85 c unless otherwise specified. table 18. adc electrical characteristics symbol parameter test conditions value unit min typ max res resolution sinewave with ? v in amplitude 12 bits ? v in input voltage range 0 2.5 v f mod modulator oversampling fre- quency 2.1 mhz ibw input bandwidth f mod / 4096 khz n ch number of input channels 4 n pbr passband ripple 0.1 db sinad s/n and distortion 56 63 db thd total harmonic distortion 60 74 db z in input impedance f mod = 2 mhz 1 m ? c in input capacitance 5 pf i adc power consumption t a = 27 c 2.5 3.0 ma i stby standby power consumption t a = 27 c 1 a
str71xf - package characteristics 35/39 3 package characteristics 3.1 package mechanical data figure 17. 64-pin thin quad flat package (10x10) figure 18. 144-pin thin quad flat package dim. mm inches min typ max min typ max a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.17 0.22 0.27 0.007 0.009 0.011 c 0.09 0.20 0.004 0.008 d 12.00 0.472 d1 10.00 0.394 e 12.00 0.472 e1 10.00 0.394 e 0.50 0.020 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 number of pins n 64 a a2 a1 c h l1 l e e1 d d1 e b dim. mm inches min typ max min typ max a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.057 b 0.17 0.22 0.27 0.007 0.011 c 0.09 0.20 0.004 0.008 d 21.80 22.00 22.20 0.858 0.867 0.874 d1 19.80 20.00 20.20 0.780 0.787 0.795 d3 17.50 0.699 e 21.80 22.00 22.20 0.858 0.867 0.874 e1 19.80 20.00 20.20 0.780 0.787 0.795 e3 17.50 0.699 e 0.50 0.020 k 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 number of pins n 144 a a2 a1 b c 36 37 72 73 108 109 144 e1 e d1 d 1 h b l l1 seating plane 0.10mm .004 in. e e3 d3
str71xf - package characteristics 36/39 3.2 thermal characteristics the average chip-junction temperature, t j , in degrees celsius, may be calculated using the following equation: t j = t a + (p d x ja )(1) where: ?t a is the ambient temperature in c, ? ja is the package junction-to- ambient thermal resistance, in c/w, ?p d is the sum of p int and p i/o (p d = p int + p i/o ), ?p int is the product of i dd and v dd , expressed in watts. this is the chip internal power. ?p i/o represents the power dissipation on input and output pins; most of the time for the applications p i/o < p int and may be neglected. on the other hand, p i/o may be significant if the device is configur ed to drive continuously external modules and/ or memories. an approximate relationship between p d and t j (if p i/o is neglected) is given by: p d = k / (t j + 273c) (2) therefore (solving equations 1 and 2): k = p d x (t a + 273c) + ja x p d 2 (3) where: ? k is a constant for the particular part, which may be determined from equation (3) by meas- uring p d (at equilibrium) for a known t a. using this value of k, the values of p d and t j may be obtained by solving equations (1) and (2) iteratively for any value of t a . table 19. thermal characteristics symbol parameter value unit ja thermal resistance junction-ambient tqfp 144 - 20 x 20 mm / 0.5 mm pitch 42 c/w ja thermal resistance junction-ambient tqfp 64 - 10 x 10 mm / 0.5 mm pitch 45 c/w
str71xf - order codes 37/39 4 order codes table 20. order codes partnumber flash kbytes ram kbytes emi usb can i/o ports package temp. range str710fz1t6 128+16 16 yes yes yes 48 tqfp144 20x20 -40 to +85c str710fz2t6 256+16 64 yes yes yes 48 STR711Fr1t6 128+16 16 no yes no 30 tqfp64 10x10 STR711Fr2t6 256+16 64 str712fr1t6 128+16 16 no yes 32 str712fr2t6 256+16 64
str71xf - revision history 38/39 5 revision history table 21. revision history date revision description of changes 17-mar-2004 1 first release 05-apr-2004 2 updated ?electrical characteristics? on page 21 08-apr-2004 2.1 corrected str712f pinout. pins 43/42 swapped. 15-apr-2004 2.2 pdf hyperlinks corrected. 7-jul-2004 3 corrected description of stdby, v18, vss18 v18bkp vssbkp pins added iddrun typical data updated bspi ma x. baudrate. updated ?external memory bus timing? on page 29 29-oct-2004 4 corrected flash sector b1f0/f1 address in figure 6 on page 19 corrected table ?, ?output: od = open drain (logic level) pp = push- pull t = true od, (p-buffer and protection diode to vdd not implement- ed), 5v tolerant.,? on page 11 tqfp64 test pin is 16 instead of 17. added to tqpfp64 column: pin 7 booten, pin 17 v 33io-pll changed description of jtck from ?external pull-down required? to ?ex- ternal pull-up or pull down required?. 25-jan-2005 5 changed ?product preview? to ?preliminary data? on page 1 and 3 renamed ?pu/pd? column to ?reset state? in table ?, ?output: od = open drain (logic level) pp = push-pull t = true od, (p-buffer and pro- tection diode to vdd not implemented), 5v tolerant.,? on page 11 added reference to str7 flash programming reference manual
str71xf - revision history 39/39 notes: information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2005 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia ? belgium - brazil - canada - china ? czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

▲Up To Search▲

Price & Availability of STR711F

	To Download STR711F Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .